The present invention relates to a pad signal detecting circuit in a semiconductor device, and more particularly, to a pad signal detecting circuit for detecting a reference voltage input to a pad of a semiconductor device. This invention is particularly applicable to high speed terminated interfaces using a reference voltage, such as those using Stub Series Termination Logic (SSTL). The invention allows the manufacture of semiconductor devices having more than one type of interface, because the device can sense the type of interface which is connected to the pad and activate the appropriate interface circuitry. This feature eliminates the need to manufacture different devices for different types of interfaces, and it facilitates high volume and low cost production of semiconductor devices that are compatible with more than one type of interface circuitry.
It is well-known that the operating clock speed of the central processing unit (CPU) in computers has increased substantially. The increased CPU operating speed requires that the peripheral devices connected to the CPU, such as semiconductor memory devices and application-specific integrated circuits, must also operate at a high speed. The high-speed operating requirements are satisfied to a certain extent by semiconductor memory devices such as synchronous dynamic random access memory (SDRAM) and RamBus DRAM (RDRAM).
Despite the development of high speed peripheral devices, the lack of a high speed data bus for connecting the devices with the CPU and with each other is an obstacle to the implementation of high-speed computers. In addition, the time required to transmit signals via a data bus increases with a longer bus. To overcome this problem, the Transistor Transistor Logic (TTL) level interface has been replaced by terminated interfaces which use signals referenced to a reference voltage Vref rather than to a ground voltage. There are many types of interfaces that use a reference voltage Vref, such as Stub Series Termination Logic (SSTL), Terminated Low Voltage TTL (T-LVTTL), Gunning Transceiver Logic (GTL), and High Speed Transceiver Logic (HSTL). Typical values of Vref for these interfaces are 1.5 volts, 1.5 volts, 0.8 volts, and 0.75 volts, respectively.
One type of SSTL interface has been defined by the Electronic Industries Association EIA/JEDEC standard number JESD8-8, which is incorporated by reference herein. The SSTL interface is a terminated high-speed interface, so the actual signal voltages are dependent in part on the terminated impedance of the signal lines, such as 25 ohms or 50 ohms. The SSTL signals are referenced to a voltage Vref, which is set at Vref=0.45.times.Vdd. Therefore, for a Vdd of 3.3 volts, Vref=0.45.times.3.3=1.5 volts. The SSTL "high" and "low" signals are above and below Vref, and they are specified differently for steady-state DC operation and for AC operation. DC operation requires input voltages which are Vref+200 millivolts for a high and Vref-200 millivolts for a low. AC operation requires input voltages which are Vref+400 millivolts for a high and Vref-400 millivolts for a low. For example, in a 3.3 volt system terminated at 50 ohms, Vref is 1.5 volts, a SSTL "high" input signal is 1.9 volts, and a SSTL "low" input signal is 1.1 volts.
In terminated interfaces using a reference voltage, such as SSTL, the small voltage swing about Vref facilitates implementations that run at clock speeds greater than 100 MHz. The decreased voltage swing not only facilitates higher speed, it also reduces the operating power required to drive the interface and thereby lowers the operating temperature of semiconductor devices using this type of interface.
Semiconductor devices that operate with multiple types of interfaces, including at least one of which uses a reference voltage, require a Vref detecting circuit. In this type of application, a circuit for detecting Vref applied to a pad in a semiconductor device is termed a pad signal detecting circuit.
FIGS. 1A and 1B are circuit diagrams of conventional pad signal detecting circuits in a semiconductor device. FIG. 1A illustrates a Vss detecting circuit and FIG. 1B illustrates a Vcc detecting circuit.
In FIG. 1A, a single pad 11, a PMOS transistor 13, and three inverters 15, 17, and 19 connected in series are arranged in a semiconductor device 1. The drain of the PMOS transistor 13 is connected to the pad 11, its gate is grounded, and its source is connected to a power source Vdd. The drain of the PMOS transistor 13 is also connected to the input terminal of the first inverter 15, and an output signal PDET is generated by the output terminal of the third inverter 19. PMOS transistor 13 is a long channel transistor, so it acts as a resistance element.
The circuit shown in FIG. 1A operates as follows. When a voltage of a logic high level, for example Vdd, is input to the pad 11, it is inverted three times while passing through three inverters 15, 17, and 19. Therefore, PDET is set to a logic low level, or false output state. On the other hand, if a voltage of a logic low level, for example Vss, is input to the pad 11, the input of first inverter 15 is pulled to a logic low level and PDET is set to a logic high level, or true output state. Here, the PMOS transistor 13 prevents PDET from being true (high) when the pad 11 is disconnected from a peripheral device, and thus it supplies a voltage of a logic high level to the first inverter 15 when the pad is in an open circuit state. As described above, the circuit of FIG. 1A detects an input of Vss to pad 11 so that PDET is set to a high level (true) when Vss is applied to the pad.
In FIG. 1B, the semiconductor device 1 contains the pad 11, an NMOS transistor 21, and three inverters 15, 17, and 19 connected in series. The drain of the NMOS transistor 21 is connected to the pad 11, its gate is connected to Vdd, and its source is grounded. The drain of the NMOS transistor 21 is connected to the input terminal of the first inverter 15, and an output signal PDETB is generated by the output terminal of the third inverter 19. NMOS transistor 21 is a long channel transistor, so it acts as a resistance element.
The circuit shown in FIG. 1B operates as follows. When Vdd is input to the pad 11, it is inverted three times while passing through three inverters 15, 17, and 19. Thus, PDETB is set to a logic low level, or true output state. When Vss is input to the pad 11, or pad 11 is connected to an open circuit, PDETB is set to a logic high level, or false output state. As described above, the circuit of FIG. 1B detects an input of Vdd to pad 11 so that PDETB is set to a logic low level (true) when Vdd is applied to the pad.
However, if Vref of 1.0 V, for example, is input to pad 11 in FIGS. 1A and 1B, the inverters 15, 17, and 19 malfunction. The malfunction is described below in connection with the detailed circuit diagram of an inverter shown in FIG. 2.
In FIG. 2, if a Vref of 1.0 V is input to an input terminal 23, a PMOS transistor 25 and an NMOS transistor 27 are simultaneously activated. This allows current to flow directly from Vdd to ground through the PMOS and NMOS transistors 25 and 27, thereby increasing the power dissipation of the interface circuitry. Furthermore, the voltage at an output terminal 29 is set to an intermediate level which is neither a logic high level nor a logic low level, due to the activation of both PMOS and NMOS transistors 25 and 27. As a result, the inverter does not perform the expected function of inverting the signal present at its input terminal 23.
As described above, an input of Vdd or Vss to a pad 11 can be detected in the prior art, whereas an input of Vref to the pad 11 is not properly detected. Therefore, interfaces using Vref generally cannot be connected to a semiconductor device having conventional interface circuitry. This invention allows the manufacture of semiconductor devices having more than one type of interface, because the device can sense the type of interface that is connected to the pad 11 and activate the appropriate interface circuitry. This feature eliminates the need to manufacture different devices for different types of interfaces, and it facilitates high volume and low cost production of semiconductor devices that are compatible with more than one type of interface circuitry.